1. Field of the Invention
The present invention relates to the control of a photosensitive cell made in monolithic form of an image sensor intended to be used in shooting devices such as, for example, shooting cameras, camcorders, digital microscopes, or digital cameras. More specifically, the present invention relates to a photosensitive cell based on semiconductors.
2. Discussion of the Related Art
FIG. 1 schematically shows the circuit of a photosensitive cell of a photosensitive cell array of an image sensor. With each photosensitive cell of the array are associated a precharge device and a read device. The precharge device is formed of an N-channel MOS transistor M1, interposed between a supply rail Vdd and a read node S. The gate of precharge transistor M1 receives a precharge control signal RST. The read device is formed of the series connection of two N-channel MOS transistors, M2, M3. The drain of first read transistor M2 is connected to supply rail Vdd. The source of second read transistor M3 is connected to input terminal P of an electronic processing circuit (not shown). The gate of first read transistor M2 is connected to read node S. The gate of second read transistor M3 is capable of receiving a read signal RD. The photosensitive cell comprises a charge storage diode D1 having its anode connected to a reference supply rail or circuit ground GND and its cathode directly connected to node S. The photosensitive diode comprises a photodiode D2 having its anode connected to reference supply rail GND and its cathode connected to node S via an N-channel charge transfer MOS transistor M4. The gate of charge transfer transistor M4 is capable of receiving a charge transfer control signal T. Generally, signals RD, RST, and T are provided by control circuits not shown in FIG. 1 and can be provided to all the photosensitive cells of a same row of the cell array.
FIG. 2 shows an example of a timing diagram of signals RD, RST, T, and of voltage VRD at node S of the circuit of FIG. 1 for a read cycle of the photosensitive cell of FIG. 1. Signals RD, RST, and T are binary signals varying between high and low levels that can be different for each of the signals.
Between two read cycles of the photosensitive cell, signal T is low. Transfer transistor M4 is thus off. The lighting causes the forming and the storage of charges at the level of photodiode D2. Further, signal RST is high. Precharge transistor M1 is thus on. Voltage VRD is then substantially equal to voltage Vdd.
At a time t0, the array row containing the photosensitive cell to be read is selected by setting, to the high level, signal RD. The precharge of read node S is interrupted by setting at time t1 signal RST to the low state, thus turning off precharge transistor M1. Voltage VRD at read node S is then set to a precharge level VRST which can be lower than voltage Vdd due to a coupling with precharge transistor M1. Precharge level VRST is generally disturbed by noise essentially originating from the thermal noise of the channel of precharge transistor M1. This noise is sampled and maintained on charge storage diode D1 upon turning-off of precharge transistor M1. Precharge level VRST is then stored outside of the photosensitive cell via read transistors M2, M3.
At time t2, signal T is set to the high state. Transfer transistor M4 is then on; which enables transfer of the charges stored in photodiode D2 to read node S. Photodiode D2 is designed so that all the charges stored therein are transferred to read node S. Voltage VRD then decreases to reach a wanted signal level VRD. Once the charge transfer has been performed, signal T is set at time t3 to the low level, thus enabling isolating photodiode D2 again and resuming a cycle of charge forming and storage due to the lighting. Desired signal level VRD is then read via read transistors M2, M3. Like precharge level VRST, desired signal level VRD is especially disturbed by the thermal noise of the channel of precharge transistor M1, which has been sampled and maintained on charge storage diode D1. The subtraction of signals VRD and VRST by the processing circuit enables suppressing the noise of precharge transistor M1 by a double correlated sampling. Once the reading is over, signal RST is set to the high state at time t4 to precharge read node S again. Finally, at time t6, signal RD is set to the low state to deselect the photosensitive cell.
It is possible for diode D1 not to be formed by a specific component. The function of storing the charges originating from photodiode D2 is then ensured by the apparent capacitance at read node S which is formed of the capacitances of the sources of transistors M1 and M4, of the input capacitance of transistor M2, as well as of all the stray capacitances present at node S.
FIG. 3 illustrates, in a partial simplified cross-section view, an implementation in monolithic form of the assembly of photodiode D2 and of transfer transistor M4 of FIG. 1. These elements are formed in a same active area of a lightly-doped semiconductor substrate 1 of a first conductivity type, for example, type P (P−). This substrate for example corresponds to an epitaxial layer on a silicon wafer which forms reference supply rail GND. The active area is delimited by field insulation areas 2, for example, made of silicon oxide (SiO2), and corresponds to a well 3 of the same conductivity type as underlying substrate 1, but more heavily doped. Above the surface of well 3 is formed an insulated gate structure 4 possibly provided with lateral spacers. On either side of gate 4, at the surface of well 3, are source and drain regions 5 and 6 of the opposite conductive type, for example, N. Drain region 6, to the right of gate 4, is heavily doped (N+). Source region 5 is formed on a much larger surface area than drain region 6 and forms with underlying substrate 3 the junction of photodiode D2. Gate 4 and drain 6 form one piece with metallizations (not shown) which enable putting these regions in contact respectively with transfer control signal T and the gate of transistor M2 (node S). The structure is completed by heavily-doped P-type regions 8 and 9 (P+). Regions 8 and 9, underlying areas 2, are connected to the reference or ground voltage via well 3 and substrate 1. Photodiode D2 is of the so-called completely depleted type and comprises, at the surface of its source 5, a P-type region 7, shallow and more heavily doped (P+) than well 3. Region 7 is in lateral (vertical) contact with region 8. It is thus permanently maintained at the reference voltage level.
FIG. 4 schematically illustrates the voltage levels of the different regions of FIG. 2. The curve in strip-dot lines illustrates the system state just after time t2. Heavily-doped P-type regions 7, 8, and 9 are permanently maintained at the reference or ground voltage, for example, 0 V. Region 5 of photodiode D2, completely charged, is at a voltage VDC. Transistor M4 is on. Channel region 3 of transistor M4 is at a voltage VTR. Region 6 corresponding to node S is at precharge level VRST. Between times t2 and t3, the charges accumulated in region 5 are transferred to region 6. The curve in full line illustrates the system state just after time t3. The charges stored in photodiode D2 being completely transferred to node S, photodiode D2 reaches a so-called depletion quiescent level VD set by the sole characteristics of photodiode D2. Transfer transistor M4 being off, channel region 3 is at 0 V. Region 6 is at the level of wanted signal VRD. Region 5 of photodiode D2 then forms an empty potential well which refills according to the photodiode lighting.
Generally, the high level of transfer control signal T applied to the gate of transfer transistor M4 is such that the voltage in channel region 3 of transistor M4 is intermediary between depletion level VD, and wanted signal level VRD, in such voltage conditions.
For denser and denser technologies with photosensitive cells of small dimensions and lower and lower control signals, it becomes difficult to ensure a good charge transfer from photodiode D2 to read node S.
To improve the charge transfer, it is possible to increase the high level of signal T applied on the gate of transfer transistor M4 to increase the intensity of the electric field enabling the charge flow. However, if the level of the channel of transfer transistor M4 becomes relatively too high with respect to supply voltage Vdd, charges may be stored during the charge transfer in channel region 3 of transfer transistor M4 due to the capacitive character of transistor M4. Charges can thus be sent back to photodiode D2 at the falling edge of signal T from the high level to the low level at time t3. This may translate as an error on the measured wanted signal level VRD and result in a so-called “trailing” effect upon successive readings of a photosensitive cell, due to the reading of residual charges of the previous image upon reading of the next image.